GPS: The Challenge of a Single Chip

The idea of integrating a complete GPS receiver onto a single chip has taken on some of the same character as the search for the Holy Grail. And, as with that legendary tableware, a school of thought exists as to whether such a thing could ever truly exist in the real world.

As a matter of physics, the GPS single-chip challenge (including processor, memory and peripherals) can most certainly be met given the current state of technology – for a price. As a matter of business, it may not be a challenge that many GPS manufacturers and system developers would want to take up.

Indeed, the vision of a $5 GPS chip being plucked casually off the shelf obscures or ignores the large investment needed to underwrite the cost of initial development for an integrated circuit (IC) chip. It doesn’t reflect the recurring costs involved in different types of integration. And it also begs the question of whether a sufficient market exists that really needs this integration and can recover both the initial fixed costs for development as well as the recurring costs of manufacturing.

In some application markets, economies of scale will never occur that would justify a single chip solution. Other levels of integration using other form factors, such as multichip modules, boards, or even complete end-user systems, certainly make more sense for many of these segments. In these commercial calculations, the product price point acts as the fulcrum on which companies seek to balance costs (plus profit margin) with prospective markets and sales levels. So, before one can answer the challenge of how such a product can be made technically, a company must demonstrate that it makes business sense to do so.

Figure 1 Generic schematic of key GPS receiver components

With those issues in mind, this article will outline the key components, costs, the benefits of integration, and the most likely approaches to GPS chip-level integration.

GPS Building Blocks

The integration trend in the modern electronics industry seeks to achieve one or more of the following: lower cost, smaller size, reduced power consumption, ease of manufacturing, and increased reliability. When it comes to a GPS chip, most manufacturers and users would like all this without sacrificing any of the other features of GPS equipment that we’ve come to enjoy: accuracy, availability, flexibility, and so forth.

To understand how integration decisions can affect these objectives in the GPS world, we should first consider the basic components or modules of a GPS receiver and their relative size, cost, and power consumption. (The cost figures mentioned in the following outline refer to the cost that a GPS manufacturer incurs and not the selling price for a finished product. The low-end manufacturing cost figures assume annual quantities of more than 100,000 units and, for high-end products, annual quantities of about 5,000.)

A GPS receiver consists of the following modules (see Figure 1):

Antenna element. This section receives the GPS signal. The cost of a GPS antenna element varies from $3 to $300 based on the characteristics of the antenna, such as phase center stability and single- versus double-frequency signal reception. This component consumes no power. The diameter of the element is between 2 and 15 centimeters depending on the substrate and the number of frequencies tracked. The antenna element cannot easily be integrated into a chip along with other modules; so, we will not pursue it further in this discussion.

Low noise amplifier (LNA). The LNA amplifies the GPS signals. The cost of this module varies from $5 to $100 depending on the number of frequencies and the quality of filters used. The amplifier portion ($3 to $20) can be integrated into a chip with the radio frequency (RF) section; but filters, which account for most of the cost ($2 to $80), must be external (not integrated with the chip). The size of an LNA varies from 2 to 20 square centimeters (cm2), depending on the number of frequencies and quality of filtering. Similarly, power consumption varies from 20 milliwatts (mW) to 200 mW.

Antenna housing. If the antenna is not integrated with the receiver, it needs a housing that costs from $10 to $50 depending on quality.

RF section. The RF downconverts the received L-band GPS signal to a lower (intermediate) frequency and then to its digital form. Direct sampling of the GPS signal at its broadcast frequencies can eliminate this stage. Direct sampling, however, faces the challenge of designing narrow-aperture and more demanding digital signal processing. Moreover, direct sampling may not offer any advantage when low-cost, mixed-mode chips (that is, analog and digital) become a reality.

The RF section typically costs from $5 to $200, depending on the number of frequencies and the quality of the filters used. As with the LNAs, the RF filters that account for most of the cost ($3 to $150) must be external. The size of the RF section varies from 2–30 cm2, depending on the number of frequencies, down-conversion plans, quality of filtering, and miscellaneous functions such as in-band interference rejection. Power consumption varies from 100 mW to 1 Watt.

Digital section. This part, commonly referred to as the “GPS chip” in each manufacturer’s receiver, processes the digital samples and provides fundamental tracking measures.

Such chips typically cost between $5 and $15, depending on the chip’s complexity and whether the receiver provides single- or dual-frequency tracking.

From the information presented thus far and what we will discuss later, it becomes clear that the cost of the “GPS chip” is a small fraction of a GPS receiver’s total cost. The size of the actual chip varies from 232 millimeters (mm) to 535 mm; however, the packaging of the chip that allows pins to be attached to the chip increases these dimensions. The size of the packaged chip varies from 131 cm to 333 cm. The number of pins also varies from about 50 to 300.

Microprocessor. This section includes a microprocessor to perform several tasks:

• 1. control the tracking elements (loops) of the digital section based on the tracking measurements of the measured ranges and Doppler (range rate changes) of satellite
• 2. collect navigation (NAV) data of the GPS signal that includes information about the orbit and clock of each satellite, among many other things
• 3. aid and speed satellite tracking by providing information to the tracking loops
• 4. compute position and velocity based on the range and Doppler measurements and satellite orbits
• 5. perform additional in-receiver calculations such as real-time kinematic (RTK) techniques that use carrier phase measurements
• 6. support the user interface that controls the keyboard, display, and interaction with the user.

The expense of a microprocessor is between $5 and $50, depending on its processing power. For example, if a receiver is to provide real-time kinematic (RTK) solutions at the rate of 20 times per second, it needs a powerful microprocessor that costs more towards $50. Microprocessor chip sizes vary from 131 cm to 333 cm. Power consumption varies from 200 mW to 3 W.

Processor peripherals. These peripherals provide memory for program and data storage as well as program execution. This section typically costs between $5 and $100, depending on the capacity and speed of the components. Some microprocessors include a fair amount of peripherals and I/Os. The size of this section varies from 10 to 100 square centimeters (cm2), depending on the size and type, as well as any special features. Power consumption varies from 100 mW to 2 W.

Figure 2 Relative sizes of GPS packaged die and chips

I/O and drivers. These consist of elements such as serial, parallel, USB, Ethernet, and other communication ports. Costs vary from $2 to $20, depending on the number and type of ports. The size of these elements can range from 1 cm2 to 10 cm2 depending on the type and number of I/Os. Power consumption ranges from 10 mW to 100 mW.

Display. Here users view the information resulting from receiver operation. A display costs between $5 and $200, depending on the size, resolution, and color. The front- or backlighting feature also can cost from $1 to $20 depending on the method and brightness. A touchpad (additional cost of $5 to $20) can be integrated on top of the display. The size of display varies from a few characters to a full Video Graphics Array (VGA) screen. As a compromise to ensure a reasonably portable size and good graphics, enduser GPS equipment commonly incorporates VGA or Super VGA for applications that require map graphics. The power consumption of displays varies from a few milliwatts to 2W. Frontlighting or backlighting (depending on the display type) usually presents a challenge because indoor and outdoor readability of displays present conflicting requirements.

Keyboard. Users convey their commands to the GPS equipment by this familiar means. Keypads are commonly integrated within the display on units with a touchpad screen. Cost per keypad ranges from $1 to $20. The size and shape of keyboards depend on particular applications. Keyboards use almost no power.

Connectors. These commonly include antenna (if not integrated in the same box), power, and data connectors. Connectors could actually be the most expensive parts of a receiver, depending on the applications for which the equipment is designed. The waterproof connectors cost between $5 and $20. Each connector has an internal connection to the receiver and requires an external plug and cable. A set of serial cables can easily cost $50. A set of high-quality waterproof connectors in a GPS receiver can add $200 to its cost .

Power supplies. Different voltages must reach the various sections of the receiver from a single power source, either batteries or an external input. Electronic circuits must receive “clean” and exact voltages. The power supply section receives power from external sources that are typically not constant (for example, battery voltage can change over time) or not clean (for example, external supplies are noisy) and regulates them for the use of the various electronic circuits. Designing all the circuits to use the same voltage has the advantage of making the design of the power supplies simpler and less expensive. One may integrate all components in a single chip; however, if the chip requires two different voltages, the extra size of the power supply will more than offset the savings of chip integration.

Rechargeable battery and charger. Battery and chargers account for a good portion of the size and weight of a GPS receiver. One may expend a lot of effort in reducing the size of the electronic circuitry but lose it all in the size of the battery needed, if the electronics use a lot of power. This section can cost from $10 to $50 depending on the capacity and type of the battery. An internal or external charger costs from $5 to $20, depending on the quality and the power management scheme used (for internal chargers).

Board assembly and integration. This consists of the printed circuit boards that hold all the components and interconnects. These costs range from $10 to $200, again depending on the complexity of the receiver board.

Enclosure. This box holds the components described here. Injection moldings or extrusions require some initial set-up costs but make the enclosures amazingly inexpensive (at least compared to connectors). An enclosure can cost from $2 to $20, depending on quality and any requirement to be waterproof.

These numbers show that the cost of building a complete GPS receiver can range from $70 to $1,500, with a selling price from less than $100 up to $15,000. The main reason for the high selling price of high-end receivers is

their typically low production quantities. If the quantity became reasonably high, the cost of even the most advanced and complete GPS receiver could easily drop to $3,000.

Benefits of Integration

With this descriptive outline of receiver components complete, we can now study the GPS integration issue.

Chip-level integration provides a variety of benefits to manufacturers and system integrators. Here are some of the most important ways:

How integration reduces size. The actual size of a chip (for example, a silicon die) is a small fraction of the packaged chip. When the packaged chips are mounted on a PC board, they require additional space for routing the circuit lines between them. When the functions of two chips are integrated into one, the size of the packaged chip may not change at all, and thus can reduce the size of the PC board space by more than half. Figure 2 shows the relative sizes of the packaged die and the packaged chip.

How integration improves reliability. Solder points of pins (leads) of chips to PC boards are one of the main issues affecting product reliability. Each soldered pin represents a potential failure point. Hence, reducing the number of chips on a PC board improves reliability.

How integration reduces cost. If 10 chips that each cost $5, for example, get integrated into a single chip, the cost of the integrated chip may be on the order of $10. Additional savings come from the resulting efficiencies in board assembly. The reduction in size, complexity of the board layout, purchasing, stocking, and mounting of 1 chip instead of 10 can significantly lower overall costs. Fewer chips also significantly reduce the risk of component shortages in the market.

How integration reduces power consumption. A significant portion of power consumption of chips is related to amplifiers that provide enough power for the signals to exit the pins of the chips. If the signals are used locally in the same chip, then the need to amplify the output signals disappears. Power consumption can be cut in half if such amplifiers are eliminated. This is particularly true in RF chips. Lower signal power also reduces the danger of radiating noise to other sections of the board. (When people talk quietly with each other inside a small room, they don’t disturb others . Compare this with people shouting to each other from rooms that are far apart!)

How integration affects performance. Integra-tion typically improves the performance of digital sections. Digital signals have enough tolerance for noise that integrating many functions has no negative impact on performance. Short lines in a chip allow higher speed and lower power consumption. RF chips require extreme care to ensure that proximity of other signals does not degrade performance. Integration can protect against signals propagating outside the chip (consider the room example mentioned earlier). This improves performance. But the proximity of RF signals inside a chip can degrade the performance. The combination of very careful design, black magic, and luck can provide the desired result! Successfully integrating digital and analog signals in the same chip requires a lot more of this black magic and luck!

One prominent technical challenge arises from the “mixed-mode” integration of the high frequency LNA and RF section, (which are in high-frequency analog form) with the other modules that operate in digital form. Integrating the LNA and RF with all of the other modules can be very expensive and also raises the danger of interference between the RF and digital signals that reside close together in a small substrate (with separation distances of a few millimeters).

Integration Scenarios

Let’s consider the varieties of integration that are feasible today. Of the previously discussed elements, the candidates for chip-level integration are LNA, RF section, digital section, microprocessor, microprocessor peripherals, and I/O and drivers. All of these features can feasibly be incorporated into a single chip; it is only a matter of initial investment.

In the following list, each pair of paren-theses denotes a chip. A plus sign appearing between parentheses indicates a single-chip combination. For example, (LNA1RF) means LNA and RF in one chip.

(LNA) (RF) (Digital) (Microprocessor) (Micro-processor peripherals) (I/O and Drivers). In this configuration, the LNA and RF are built from discrete components (for example, amplifiers and mixers). The digital component is a single chip that typically represents the proprietary technology of a GPS company. It can have single- or multiple-frequency processing of GPS or GPS in combination with GLONASS or other systems.

This scenario is the most common for high-end precision applications such as survey. The manufacturer focuses on improving the performance of the receiver portion and buys other components off the shelf. The complex signal processing requires a powerful microprocessor and a lot of memory. When combined with low product volume (currently fewer than 20,000 a year), this does not justify the huge initial investment required for greater integration. New and more powerful processors become available each year. Little benefit exists in trying to integrate these incrementally smaller processors into products unconstrained by size limitations and with low-volume production. Time to market also prohibits integrating most components in a high-end system.

The initial cost of making a digital GPS chip ranges from $100,000 to $500,000. This does not include the R&D cost of designing the GPS circuitry, but is merely the cost of transferring the design to a chip. The same applies to the “initial cost” in the following sections. It is impossible to make a reasonably sized GPS receiver without integrating the GPS digital section into a chip. Only a few prototype receivers were built with discrete digital parts in the early days of GPS (1980).

(LNA1RF) (Digital) (Microprocessor) (Micro-processor peripherals) (I/O and Drivers). Combining LNA and RF components is typically the first step in GPS receiver integration. This configuration is commonly implemented in handheld and navigation products that are not sensitive to factors such as phase jitter. All existing integrated LNA and RF chips have lower performance than those designed with discrete components. Currently, hardly any high-end receiver uses integrated RF chips. The initial cost in designing an LNA1RF chip is from $150,000 to $500,000. That chip’s unit cost falls to less than $5 in quantities of 100,000.

(LNA1RF1Digital) (Microprocessor1I/O and Drivers) (Microprocessor peripherals). Another stage of integration combines digital and analog sections. This is the big technical challenge discussed earlier. The initial cost of designing such a chip is on the order of $500,000. The resulting chip’s unit cost in high volume is on the order of $10 to $20.

As we have already seen, high-end multiple frequency applications are not good candidates for such integration. Most navigation or single-frequency applications, however, do not require a very powerful processor. Off-the-shelf medium-power processors exist that also include I/O and drivers. Microprocessor peripherals are off-the-shelf components that could cost around $10.

(LNA1RF) (Digital1Microprocessor1I/O and Drivers) (Microprocessor peripherals). Another scenario integrates the LNA and RF components in one chip and digital, microprocessor, and I/O in another. This approach poses no technical risk; the main issue revolves around the initial investment of developing such chips. The Digital1Microprocessor1I/O chip may need an initial investment of about $500,000. Companies that lack a design for a microprocessor typically must license one. The license cost can reach $1 million plus a royalty of a few dollars for each part.

(LNA1RF) (Digital1Microprocessor1Microprocessor peripherals1I/O and Drivers). This scenario comprises the largest integration of digital elements with sufficient memory also integrated into the chip. The integration of memory not only helps to reduce the power consumption but also increases memory access speed by eliminating the input/output delay to and from the chips.

Chip technology available today makes this the most attractive integration scenario. The cost of the integrated digital is between $15 to $20. This scenario offers substantial savings in cost, PC board space, and power consumption without significant technology risk. The chip in a 0.18 micron design can be 14315 mm.

The layout of such a chip could be a challenge with an initial development cost of between $500,000 and $1 million, not counting the initial license fee for the microprocessor (in case the company does not have it). This integration makes most sense for handheld and navigation applications where size and power consumption are critical.

(LNA1RF1Digital1Microprocessor1Microprocessor peripherals1I/O and Drivers). This is the ultimate integration. However, the advantages of reducing two chips to one are very small compared to the technical risk, loss of performance, and increase in cost. The initial design can cost more than $2 million, and may take a very long time to develop. The parts cost can easily exceed $50 per unit. By the time such development is complete, the design may have become obsolete due to technology changes.

Multichip modules. So far we have discussed integrating functions into the same chip and substrate. In multichip module technology, several substrates may be packaged in the same chip enclosure. For example, in the last configuration described in the previous section, the RF chip may be mounted on one substrate and all other parts in another. But both substrates are housed inside the same enclosure, and it will look like a single chip to users. This technique loses its attractiveness as the techniques of mounting substrates directly onto PC boards (without chip packaging) become inexpensive and popular.

Integrating GPS with other products. When integrating GPS with other products, such as cell phones, many of the parts can be shared. For example, the cell phone and GPS receiver can use the same microprocessor and its peripheral, I/O and drivers, as well as the display, keypad and connectors, and power supplies. Adding cell phone features to a GPS receiver can create an additional cost of less than $10. For the digital section alone, the additional cost can be as low as $1, and $2 for the RF section.

Decision Point

Strategic decisions about undertaking an aggressive integration within GPS receivers depend largely on the applications and associated markets. For example, the automobile application cares less about the reduced power consumption and slightly smaller size of a more completely integrated GPS chip or chipset than about a few dollars’ reduction in unit cost. For avionics applications (especially high-precision approach and landing), probably no one cares about a reduction in size, a few dollars of cost savings, and relatively small reduction in power consumption.

In high-end geodetic applications, the only advantage of chip-scale integration may be related to lower power consumption, which also reduces the size and weight of batteries that must be carried into the field. Little practical or competitive advantage lies in integrations that lower by only a few dollars the price of a receiver that sells for $15,000.

The one-chip challenge for GPS applies primarily to applications in which size and power consumption is of utmost importance and the size of the market justifies the high initial cost. This includes applications such as integration into cell phones and watches. The practical benefits of such integrations appear debatable. We have seen integration of GPS in a watch that resulted in a product that is neither a good GPS receiver nor a good watch.

In 1982, a four-channel survey grade GPS receiver weighed 50 kilograms and cost $200,000. Today, the GPS industry offers 20-channel GPS/GLONASS survey grade systems (including batteries and controllers) that have much better performance, weigh less than 2 kilograms, and cost $10,000. This trend will never stop. The cost structure that we analyzed above demonstrates that the selling price of a high-quality GPS receiver can go down to $2,500 if the volume sufficiently increases. A three-fold cost reduction is on the horizon.

No good reason exists to prevent the cost of a commercial GPS receiver from eventually falling to little more than an AM/FM

handheld radio. And, as with an AM/FM radio, volume is the key!

;